Japanese Unexamined Patent Application Publication No. 2005-223171 (Patent Document 1) discloses a technology for preventing wiring congestion when scan chain groups are connected to constitute a whole scan chain in a semiconductor integrated circuit in which a plurality of scan chain groups are formed. More specifically, when individual scan chain groups are connected to constitute the whole scan chain, the connection sequence of the scan chain groups is determined in order of closeness in mutual distances of the center of gravity coordinates of all the flip-flop layout coordinates included in the respective scan chain groups. Alternately, the connection sequence of the scan chain groups is determined in order of closeness of the mutual distances of position coordinates of gated cells existent in clock systems of the scan chain groups, or in order of closeness of the mutual distances of target cells arbitrarily designated beforehand, or in order of closeness of the mutual distances of flip-flop sets, in which the mutual distances of the scan chain groups are the shortest.
Japanese Unexamined Patent Application Publication No. 2003-014818 (Patent Document 2) discloses a technology that expands the application range of a scan test by a scan test circuit from the traditional static logic failure detection up to timing failure detection at an actual operating frequency. More specifically, even in the case where arbitrary test patterns can be set on the scan flip-flops and a high failure detection rate can be secured in the static logic failure detection, the same logical values cannot be outputted simultaneously from these flip-flops at the scan test due to the relationship between the preceding stage and the subsequent stage of the flip-flops. Therefore, it is difficult to set a test pattern that detects a path delay failure, and a timing failure detection rate at the actual operation frequency cannot be increased. Hence, in a scan test circuit in which a predetermined logic signal is inputted to one input terminal of the scan chain to sequentially obtain the logic result from the output terminal of the scan chain, a plurality of flip-flops which give input values to the same logic circuit and are connected by the scan chain are arranged so as not to be adjacent to each other on the scan chain.
Japanese Unexamined Patent Application Publication No. 2005-274500 (Patent Document 3) discloses a technology for catching the failure responses even if failures simultaneously occur in a plurality of scan-out signal lines in a configuration where the number of external output pins is reduced to be smaller than the number of scan-out signal lines by interposition of a compressor in order to shorten the wiring length of the scan-out signal lines. That is, the compressor is interposed between the scan-out signal lines and the external output pins, and the compressor is configured to make a response, which is different from a response in the case where all are normal, as a response in the case where a plurality of failure responses are simultaneously input from the scan-out signal lines. More specifically, the compressor is configured of compression gates that are EXOR gates or EXNOR gates corresponding to the number of the external output pins, and all the scan-out signal lines are connected to the compression gates in the state where the patterns of input connections to the compression gates are all mutually different.
Japanese Unexamined Patent Application Publication No. 2000-055986 (Patent Document 4) discloses a technology for preventing a malfunction due to a clock skew and the like and realizing a small layout area by connecting the scan chains to be short. More specifically, scan registers are hierarchically grouped based on the clock tree configuration, and the clock signal propagation time from the clock input terminals to respective clock tree buffers and the clock signal propagation time from the clock input terminals to respective scan registers are obtained, and moreover, the clock skew is obtained for each scan register group and an attribute of the shortest wiring length or the malfunction prevention is set for each scan register group based on the clock skew information. Then, a scan chain for the purpose of malfunction prevention is connected to the scan register group to which the malfunction prevention attribute is set, and a scan chain is connected with the shortest wiring length by using the arrangement information to the scan register group to which the shortest wiring length attribute is set.    Patent Document 1: Japanese Unexamined Patent Application Publication No. 2005-223171    Patent Document 2: Japanese Unexamined Patent Application Publication No. 2003-014818    Patent Document 3: Japanese Unexamined Patent Application Publication No. 2005-274500    Patent Document 4: Japanese Unexamined Patent Application Publication No. 2000-055986